1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NFET and PFET transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. Other types of semiconductor devices include resistors, capacitors, diodes, etc. These basic semiconductor devices are arranged and configured in various electrical circuits that perform a desired function on the integrated circuit device. These integrated circuits are formed by connecting the various semiconductor devices to one another using a complex wiring system. Typically, the wiring systems are comprised on multiple metallization layers, each of which contains conductive lines and conductive vias. The conductive vias usually are the means by which the metal lines in adjacent metallization layers are conductively coupled to one another.
Improving the functionality and performance capability of various metallization systems has become important in designing modern semiconductor devices. One example of such improvements is the enhanced use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior art metallization systems using tungsten for the conductive lines and vias. The use of low-k dielectric materials also tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk as compared to other dielectric materials with higher dielectric constants. However, the use of such low-k dielectric material can be problematic as they tend to be less resistant to metal migration as compared to some other dielectric materials.
FIGS. 1A-1G depict one illustrative prior art process flow for forming conductive structures, i.e., metal lines and via, on an integrated circuit device. FIG. 1A depicts an illustrative prior art device 100 at an early stage of manufacture. The device 100 is formed above a semiconducting substrate (not shown). As shown therein, an illustrative conductive metal line 12 is formed in a layer of insulating material 10 that is formed above the substrate. The insulating layer 10 and the metal line 12 may be part of a metallization layer for an integrated circuit device that may include several metallization layers. An illustrative etch stop layer 13, an insulating layer 14 an etch stop layer 16 a metal hard mask layer 18 and a patterned mask layer 20 having an opening 22 formed therein.
The various layers depicted in FIG. 1A may be comprised of a variety of different materials and they may be formed by performing a variety of known processing operations, like chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or plasma-enhanced versions of such deposition processes, and traditional photolithography processes. In one illustrative embodiment, the insulating layers 10, 14 may be comprised of a so-called low-k insulating material (k value less than 2.7), the etch stop layer 13 may be comprised of a material known in the trade as BLOK, or any other material that will serve to protect the underlying metal line 12 when forming a via opening in the insulating layer 14. The etch stop layer 16 may also be comprised of a variety of materials such as silicon dioxide. The metal hard mask layer 18 may be comprised of a variety of metals such as, for example, titanium nitride. The patterned mask layer 20 may be comprised of one or more layers of material. In one embodiment, the patterned mask layer 20 may be a multi-layer system comprised of an organic planarization layer (OPL) formed on the metal hard mask layer 18, an anti-reflective coating (ARC) formed on the OPL and a layer of photoresist formed above the ARC layer. The opening 22 in the mask layer 20 may be formed by performing traditional photolithography and etching techniques. In the depicted embodiment, the opening 22 corresponds to the width of a metal line that will be formed in the insulating layer 14. The metal line 12 may be made of a variety of materials such as, for example, copper.
As shown in FIG. 1B, an etching process, wet or dry, is performed on the metal hard mask layer 18 to define an opening 18A therein. This etching process stops on the etch stop layer 16.
Next, as shown in FIG. 1C, the mask layer 20 is removed and a via mask layer 24 is formed on the device 100. The via mask layer 24 has an opening 24A that will be used in etching a via opening in the insulating layer 14. The via mask layer 24 may be comprised of one or more material layers. In one illustrative embodiment, the via mask layer 24 is a layer of photoresist material that is formed by performing known photolithography techniques.
Then, as shown in FIG. 1D, one or more etching process, wet or dry, is performed through the mask layer on the etch stop layer 16 and the layer of insulating material 14 to define a via opening 30 therein. Given the presence of different materials, the etch chemistry employed may need to be changed to etch through the layer 16, 14. In the depicted example this etching process stops on the etch stop layer 13. In some cases, the etching process may be controlled such that the via opening 30 does not extend all the way down to the etch stop layer 13 at this stage of the process.
Next, as shown in FIG. 1E, the via mask layer 24 is removed and one or more etching process are performed through the metal hard mask layer 18 to define a trench 40 in the layer of insulating material 14. The trench 40 may extend into and out of the drawing plane as the metal line that will be formed therein may be routed in any desired direction across the device 100. In the cross-sectional view depicted in FIG. 1E, the trench contacts via opening 30 so that the conductive via that will be formed in the via opening 30 will be conductively contact the metal line that will be formed in the trench 40. FIG. 1F is a cross-sectional view of the device 100 in a plane that is different from the plane depicted in FIG. 1E. FIG. 1F depicts only the trench 40 as it is formed in the layer of insulating material 14.
FIG. 1G depicts the device 100 after several process operations have been performed. More specifically, in FIG. 1G, an etching process is performed on the etch stop layer 13 to expose the underlying metal line 12. Thereafter, a conductive via 34 and a conductive line 32 are formed in the via opening 30 and the trench 40, respectively. The conductive via 34 and line 32 may be formed by depositing one or more barrier layers (not shown) and thereafter depositing an appropriate conductive material, such as copper across the device 100. Thereafter, a chemical mechanical polishing (CMP) process may be performed using the stop layer 16 as a polish stop to remove the conductive materials positioned outside of the trench 40 and the via opening 30. This CMP process removes the metal hard mask 18.
One problem encountered with using the prior art process described above, at least when using low-k insulating material for the layer 14, is that it may lead to the formation of undesirable voids 33 in the metal line 32, one of which is schematically depicted in FIG. 1G. With reference to FIG. 1F, during the process of forming the trench 40, the etching process tends to undercut or erode the low-k insulating material 14 in the areas identified by the reference number 26. Such undercutting is particularly noticed when reactive ion etching (RIE) process are performed in defining the trench 40. The presence of such undercut regions 26 tend to increase possibility of voids 33 in the final conductive structure, e.g., the metal line 32.
The present disclosure is directed to various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique that may at least reduce or eliminate one or more of the problems identified above.